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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9076732 B1

PDFFull Text
Date of Patent:
Jul. 07, 2015

Filed:

Sep. 27, 2012

Method to prepare semi-conductor device comprising a selective etching of a silicium—germanium layer

Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Yannick Le Tiec, Crolles, FR;

Laurent Grenouillet, Rives, FR;

Nicolas Posseme, Carantec, FR;

Maud Vinet, Rives, FR;

Assignee:

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris, FR;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Duy Deo

Int. Cl.
CPC ...
H01L 21/302 (2006.01); H01L 21/461 (2006.01); H01L 21/306 (2006.01); H01L 21/3213 (2006.01); H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); C09K 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/30604 (2013.01); H01L 21/32134 (2013.01); H01L 21/311 (2013.01); C09K 13/00 (2013.01); H01L 21/31111 (2013.01); H01L 21/823807 (2013.01); H01L 21/02057 (2013.01);
Abstract

The present invention relates to a method for manufacturing a semiconductor device by wet-process chemical etching, the device comprising at least one layer of silicon (Si) and at least one layer of silicon-germanium (SiGe) and at least one layer of photosensitive resin forming a mask partly covering the layer of silicon-germanium (SiGe) and leaving the layer of silicon-germanium uncovered in certain zones, characterized in that it comprises a step of preparation of an etching solution, having a pH between 3 and 6, from hydrofluoric acid (HF), hydrogen peroxide (HO), acetic acid (CHCOOH) and ammonia (NHOH), and a step of stripping of the layer of silicon-germanium (SiGe) at least at the said zones by exposure to the said etching solution. The invention will be applicable for the manufacture of integrated circuits and more precisely of transistors. In particular, for optimization of CMOS transistors of the latest generation.

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