The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2015
Filed:
Dec. 16, 2011
Jian-hao Chen, Hsinchu, TW;
Chia-yu LU, Hsinchu, TW;
Tung-heng Hsieh, Zhudong Town, TW;
Kuo-feng Yu, Hsinchu, TW;
Chin-shan Hou, Hsin-Chu, TW;
Hsien-chin Lin, Hsinchu, TW;
Shyue-shyh Lin, Zhubei, TW;
Jian-Hao Chen, Hsinchu, TW;
Chia-Yu Lu, Hsinchu, TW;
Tung-Heng Hsieh, Zhudong Town, TW;
Kuo-Feng Yu, Hsinchu, TW;
Chin-Shan Hou, Hsin-Chu, TW;
Hsien-Chin Lin, Hsinchu, TW;
Shyue-Shyh Lin, Zhubei, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS.). Thus, a subsequent planarization process of the dielectric layer may not contact the first gate structure.