The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2015
Filed:
Dec. 28, 2011
Sampath K. V. Karikalan, Irvine, CA (US);
Sam Ziqun Zhao, Irvine, CA (US);
Kevin Kunzhong HU, Irvine, CA (US);
Rezaur Rahman Khan, Rancho Santa Margarita, CA (US);
Pieter Vorenkamp, Laguna Niguel, CA (US);
Xiangdong Chen, Irvine, CA (US);
Sampath K. V. Karikalan, Irvine, CA (US);
Sam Ziqun Zhao, Irvine, CA (US);
Kevin Kunzhong Hu, Irvine, CA (US);
Rezaur Rahman Khan, Rancho Santa Margarita, CA (US);
Pieter Vorenkamp, Laguna Niguel, CA (US);
Xiangdong Chen, Irvine, CA (US);
Broadcom Corporation, Irvine, CA (US);
Abstract
There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The semiconductor package also includes a second active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The second portion of the first active die and the second portion of the second active die include solder balls mounted on a package substrate, and are configured to communicate electrical signals to the package substrate utilizing the solder balls and without utilizing through-semiconductor vias (TSVs).