The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2015
Filed:
Mar. 26, 2008
Applicants:
Zigmund Ramirez Camacho, Singapore, SG;
Lionel Chien Hui Tay, Singapore, SG;
Henry Descalzo Bathan, Singapore, SG;
Abelardo Jr. Hadap Advincula, Singapore, SG;
Inventors:
Zigmund Ramirez Camacho, Singapore, SG;
Lionel Chien Hui Tay, Singapore, SG;
Henry Descalzo Bathan, Singapore, SG;
Abelardo Jr. Hadap Advincula, Singapore, SG;
Assignee:
STATS ChipPAC Ltd., Singapore, SG;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 29/04 (2006.01);
U.S. Cl.
CPC ...
H01L 24/19 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3107 (2013.01); H01L 23/49524 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/20 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01033 (2013.01);
Abstract
An integrated circuit package system includes: mounting an integrated circuit die adjacent to a lead; forming a first encapsulation around and exposing the integrated circuit die and the lead; and forming a planar interconnect between the integrated circuit die and the lead with the planar interconnect on the first encapsulation.