The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 2015
Filed:
Aug. 30, 2011
Applicants:
Namju Cho, Uiwang-si, KR;
Heejo Chi, Ichon-si, KR;
Chanhoon Ko, Incheon, KR;
Inventors:
Assignee:
STATS ChipPAC Ltd., Singapore, SG;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 25/03 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49861 (2013.01); H01L 23/4985 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 25/03 (2013.01); H01L 23/49816 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/19107 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/1815 (2013.01); H01L 21/563 (2013.01); H01L 21/565 (2013.01);
Abstract
A method of manufacture of an integrated circuit packaging system includes: forming a peripheral interconnect having a bond finger and a contact pad with a trace in direct contact with the bond finger and the contact pad, the bond finger vertically offset from the contact pad; connecting an integrated circuit die and the bond finger; and forming a module encapsulation on the integrated circuit die, the bond finger and the trace exposed from the module encapsulation.