The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2015
Filed:
Sep. 27, 2012
Annalisa Cappellani, Portland, OR (US);
Pragyansri Pathi, Porland, OR (US);
Bruce E. Beattie, Portland, OR (US);
Abhijit Jayant Pethe, Hillsboro, OR (US);
Annalisa Cappellani, Portland, OR (US);
Pragyansri Pathi, Porland, OR (US);
Bruce E. Beattie, Portland, OR (US);
Abhijit Jayant Pethe, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional germanium-containing body is disposed on a semiconductor release layer disposed on the insulating structure. The three-dimensional germanium-containing body includes a channel region and source/drain regions on either side of the channel region. The semiconductor release layer is under the source/drain regions but not under the channel region. The semiconductor release layer is composed of a semiconductor material different from the three-dimensional germanium-containing body. A gate electrode stack surrounds the channel region with a portion disposed on the insulating structure and laterally adjacent to the semiconductor release layer.