The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2015
Filed:
May. 30, 2012
Timothy H. Daubenspeck, Colchester, VT (US);
Steven E. Molis, Patterson, NY (US);
Gordon C. Osborne, Jr., Essex Junction, VT (US);
Wolfgang Sauter, Hinesburg, VT (US);
Edmund J. Sprogis, Underhill, VT (US);
Timothy H. Daubenspeck, Colchester, VT (US);
Steven E. Molis, Patterson, NY (US);
Gordon C. Osborne, Jr., Essex Junction, VT (US);
Wolfgang Sauter, Hinesburg, VT (US);
Edmund J. Sprogis, Underhill, VT (US);
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Abstract
A releasable buried layer for 3-D fabrication and methods of manufacturing is disclosed. The method includes forming an interposer structure which includes forming a carbon rich dielectric releasable layer over a wafer. The method further includes forming back end of the line (BEOL) layers over the carbon rich dielectric layer, including wiring layers and solder bumps. The method further includes bonding the solder bumps to a substrate using flip chip processes. The flip chip processes comprises reflowing the solder bumps and rapidly cooling down the solder bumps which releases the carbon rich dielectric releasable layer from the wafer.