The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2015
Filed:
Sep. 28, 2011
Applicants:
IL Kwon Shim, Singapore, SG;
Kwee Lan Tan, Singapore, SG;
Jian Jun LI, Singapore, SG;
Dario S. Filoteo, Jr., Singapore, SG;
Inventors:
Il Kwon Shim, Singapore, SG;
Kwee Lan Tan, Singapore, SG;
Jian Jun Li, Singapore, SG;
Dario S. Filoteo, Jr., Singapore, SG;
Assignee:
ST ASSEMBLY TEST SERVICES LTD., Singapore, SG;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 25/065 (2006.01); H01L 21/48 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/4857 (2013.01); H01L 23/13 (2013.01); H01L 23/49816 (2013.01); H01L 25/105 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48237 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/06586 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01027 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/15165 (2013.01); H01L 2924/1517 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/1532 (2013.01); H01L 2924/15331 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01076 (2013.01); H01L 2924/014 (2013.01); H01L 2924/0132 (2013.01); Y10S 438/928 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/3511 (2013.01);
Abstract
A method of manufacturing an integrated circuit package includes: forming a substrate including: forming a core layer, and forming vias in the core layer; forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.