The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2015
Filed:
Jan. 07, 2014
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Chien Lin Ho, Taichung, TW;
Chin-Chang Hsu, Banqiao, TW;
Hung Lung Lin, Hsinchu, TW;
Wen-Ju Yang, Hsinchu, TW;
Yi-Kan Cheng, Taipei, TW;
Tsong-Hua Ou, Taipei, TW;
Wen-Li Cheng, Taipei, TW;
Ken-Hsien Hsieh, Taipei, TW;
Ching Hsiang Chang, New Taipei, TW;
Ting Yu Chen, Hsinchu, TW;
Li-Chun Tien, Tainan, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
The present disclosure relates to a method and apparatus for forming a multiple patterning lithograph (MPL) compliant integrated circuit layout by operating a construction validation check on unassembled IC cells to enforce design restrictions that prevent MPL conflicts after assembly. In some embodiments, the method is performed by generating a plurality of unassembled integrated circuit (IC) cells having a multiple patterning design layer. A construction validation check is performed on the unassembled IC cells to identify violating IC cells having shapes disposed in patterns comprising potential multiple patterning coloring conflicts. Design shapes within a violating IC cell are adjusted to achieve a plurality of violation free IC cells. The plurality of violation free IC cells are then assembled to form an MPL compliant IC layout. Since the MPL compliant IC layout is free of coloring conflicts, a decomposition algorithm can be operated without performing a post assembly color conflict check.