The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2015
Filed:
May. 08, 2012
Joanna Wasyluk, Dresden, DE;
Yew Tuck Chow, Dresden, DE;
Stephan Kronholz, Dresden, DE;
Lindarti Purwaningsih, Dresden, DE;
Ines Becker, Dresden, DE;
Joanna Wasyluk, Dresden, DE;
Yew Tuck Chow, Dresden, DE;
Stephan Kronholz, Dresden, DE;
Lindarti Purwaningsih, Dresden, DE;
Ines Becker, Dresden, DE;
GLOBALFOUNDRIES Inc., Grand Cayman, KY;
Abstract
A method and apparatus are provided for recessing a channel region of the PFET and epitaxially growing channel SiGe in the recessed region inside of a horizontally oriented processing furnace. Embodiments include forming an n-channel region and a p-channel region in a front side of a wafer and at least one additional wafer, the n-channel and p-channel regions corresponding to locations for forming an NFET and a PFET, respectively; placing the wafers inside a horizontally oriented furnace having a top surface and a bottom surface, with the wafers oriented vertically between the top and bottom surfaces; recessing the p-channel regions of the wafers inside the furnace; and epitaxially growing cSiGe without hole defects in the recessed p-channel regions inside the furnace.