The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2015

Filed:

Sep. 13, 2012
Applicants:

Donghua Liu, Shanghai, CN;

Wenting Duan, Shanghai, CN;

Wensheng Qian, Shanghai, CN;

Jun HU, Shanghai, CN;

Jing Shi, Shanghai, CN;

Inventors:

Donghua Liu, Shanghai, CN;

Wenting Duan, Shanghai, CN;

Wensheng Qian, Shanghai, CN;

Jun Hu, Shanghai, CN;

Jing Shi, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 29/737 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66242 (2013.01); H01L 29/7371 (2013.01); H01L 29/0821 (2013.01);
Abstract

A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed.


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