The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2015
Filed:
Mar. 28, 2013
Stmicroelectronics, Inc., Coppell, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Prasanna Khare, Schenectady, NY (US);
Stephane Allegret-Maret, Grenoble, FR;
Nicolas Loubet, Guilderland, NY (US);
Qing Liu, Guilderland, NY (US);
Hemanth Jagannathan, Guilderland, NY (US);
Lisa Edge, Watervliet, NY (US);
Kangguo Cheng, Schenectady, NY (US);
Bruce Doris, Slingerlands, NY (US);
STMicroelectronics, Inc., Coppell, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.