The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2015

Filed:

May. 17, 2013
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Tai-Yu Chen, Taipei, TW;

Chung-Fa Lee, Dacun Township, Changhua County, TW;

Wen-Sung Hsu, Zhubei, TW;

Shih-Chin Lin, Daxi Township, Taoyuan County, TW;

Assignee:

MediaTek Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/36 (2006.01); H01L 23/433 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/36 (2013.01); H01L 23/4334 (2013.01); H01L 23/49816 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48095 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board, having a first cross sectional dimension; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; an encapsulant layer, formed over the circuit board, covering the semiconductor chip and surrounding the spacer; a heat spreading layer, formed over the encapsulant layer and the spacer; and a plurality of solder balls, formed over the second surface of the circuit board.


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