The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2015

Filed:

Nov. 16, 2011
Applicants:

Shang-yun Hou, Hsin-Chu, TW;

Wei-cheng Wu, Hsin-Chu, TW;

Hsien-pin HU, Zhubei, TW;

Jung Cheng Ko, Taichung, TW;

Shin-puu Jeng, Hsin-Chu, TW;

Chen-hua Yu, Hsin-Chu, TW;

Kim Hong Chen, Fremont, CA (US);

Inventors:

Shang-Yun Hou, Hsin-Chu, TW;

Wei-Cheng Wu, Hsin-Chu, TW;

Hsien-Pin Hu, Zhubei, TW;

Jung Cheng Ko, Taichung, TW;

Shin-Puu Jeng, Hsin-Chu, TW;

Chen-Hua Yu, Hsin-Chu, TW;

Kim Hong Chen, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/66 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 22/14 (2013.01); H01L 21/76898 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 2224/1147 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/13124 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/13169 (2013.01); H01L 2224/0557 (2013.01);
Abstract

A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV.


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