The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Sep. 04, 2013
Applicant:

Commissariat a L'energie Atomique ET Aux Ene Alt, Paris, FR;

Inventors:

Maud Vinet, Rives sur Fure, FR;

Laurent Grenouillet, Rives, FR;

Yannick Le Tiec, Crolles, FR;

Romain Wacquez, Marseille, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/78 (2006.01); H01L 21/8242 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1248 (2013.01); H01L 21/76283 (2013.01); H01L 21/76232 (2013.01);
Abstract

A microelectronic device is provided, including: a substrate including a first semiconductor layer positioned on a dielectric layer and a second semiconductor layer; and an isolation trench disposed through the first semiconductor layer, the dielectric layer, and a part of the thickness of the second semiconductor layer, including a dielectric material and delimiting, in the first semiconductor layer, a roughly rectangular active area of the device, wherein in said part of the thickness of the second semiconductor layer, at least one portion of the dielectric material is positioned under the active area delimited by at least four side walls of the trench, and two of the at least four side walls are roughly parallel with one another and are positioned under the active area, and the other two of the at least four side walls are orthogonal to said two walls and are not positioned under the active area.


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