The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

May. 10, 2010
Applicants:

Markus Lenski, Dresden, DE;

Kerstin Ruttloff, Hainichen, DE;

Volker Jaschke, Radebeul, DE;

Frank Seliger, Dresden, DE;

Ralf Otterbach, Dresden, DE;

Inventors:

Markus Lenski, Dresden, DE;

Kerstin Ruttloff, Hainichen, DE;

Volker Jaschke, Radebeul, DE;

Frank Seliger, Dresden, DE;

Ralf Otterbach, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/8234 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823468 (2013.01); H01L 21/76837 (2013.01); H01L 21/76895 (2013.01); H01L 21/823425 (2013.01);
Abstract

In advanced semiconductor devices, spacer elements may be formed on the basis of a multi-station deposition technique, wherein a certain degree of variability of the various sub-layers of the spacer materials, such as a different thickness, may be applied in order to enhance etch conditions during the subsequent anisotropic etch process. Consequently, spacer elements of improved shape may result in superior deposition conditions when using a stress-inducing dielectric material. Consequently, yield losses due to contact failures in densely packed device areas, such as static RAM areas, may be reduced.


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