The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

May. 20, 2014
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Henry Chien, San Jose, CA (US);

Donovan Lee, Santa Clara, CA (US);

Vinod R. Purayath, Santa Clara, CA (US);

Yuan Zhang, San Jose, CA (US);

James K. Kai, Santa Clara, CA (US);

George Matamis, San Jose, CA (US);

Assignee:

Sandisk Technologies Inc., Plano, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/78 (2006.01); H01L 27/115 (2006.01); H01L 27/06 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11578 (2013.01); H01L 27/11556 (2013.01); H01L 27/0688 (2013.01); H01L 29/7889 (2013.01); H01L 29/7926 (2013.01); H01L 27/1157 (2013.01); H01L 27/11582 (2013.01);
Abstract

A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.


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