The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Nov. 26, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ravi K. Nailla, San Jose, CA (US);

John S. Guzek, Chandler, AZ (US);

Javier Soto Gonzalez, Chandler, AZ (US);

Drew W. Delaney, Chandler, AZ (US);

Hamid R. Azimi, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/56 (2006.01); H01L 23/552 (2006.01); H01L 23/64 (2006.01); H01L 23/00 (2006.01); H01L 25/16 (2006.01); H01L 23/498 (2006.01); H05K 1/18 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H01L 21/561 (2013.01); H01L 23/552 (2013.01); H01L 23/645 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/16 (2013.01); H01L 23/498 (2013.01); H01L 21/568 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/83005 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01057 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01047 (2013.01); H05K 1/185 (2013.01); H05K 3/4682 (2013.01);
Abstract

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.


Find Patent Forward Citations

Loading…