The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2015

Filed:

Nov. 07, 2007
Applicants:

Zigmund Ramirez Camacho, Singapore, SG;

Henry Descalzo Bathan, Singapore, SG;

Abelardo Jr. Hadap Advincula, Singapore, SG;

Lionel Chien Hui Tay, Singapore, SG;

Inventors:

Zigmund Ramirez Camacho, Singapore, SG;

Henry Descalzo Bathan, Singapore, SG;

Abelardo Jr. Hadap Advincula, Singapore, SG;

Lionel Chien Hui Tay, Singapore, SG;

Assignee:

STATS ChipPAC Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49548 (2013.01); H01L 21/4832 (2013.01); H01L 23/3107 (2013.01); H01L 23/49541 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/49171 (2013.01); H01L 2924/01046 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/14 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 2224/48257 (2013.01); H01L 2924/15747 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73265 (2013.01);
Abstract

An integrated circuit package system includes: forming an array of external interconnects with an intersecting region between the external interconnects; removing the intersecting region for forming an isolation hole between the external interconnects; mounting an integrated circuit die over the external interconnects; connecting an internal interconnect between the integrated circuit die and the external interconnects; and forming a package encapsulation over the integrated circuit die with the external interconnects partially exposed.


Find Patent Forward Citations

Loading…