The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2015

Filed:

Mar. 14, 2014
Applicant:

Xintec Inc., Jhongli, Taoyuan County, TW;

Inventors:

Yu-Lin Yen, Taipei, TW;

Chien-Hui Chen, Zhongli, TW;

Tsang-Yu Liu, Zhubei, TW;

Long-Sheng Yeou, Hsinchu, TW;

Assignee:

Xintec, Inc., Jhongli, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/768 (2006.01); B81B 7/00 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76879 (2013.01); B81B 7/007 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/49827 (2013.01); H01L 24/06 (2013.01); H01L 24/94 (2013.01); B81B 2207/07 (2013.01); B81B 2207/092 (2013.01); H01L 23/3178 (2013.01); H01L 24/13 (2013.01); H01L 24/32 (2013.01); H01L 25/0657 (2013.01); H01L 2221/68377 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/05669 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01014 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/014 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/14 (2013.01); H01L 2924/01021 (2013.01); H01L 2924/01033 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/9202 (2013.01);
Abstract

A method for forming a chip package, in which a substrate has a plurality of conducting pads located below its lower surface, and a dielectric layer located between the conducting pads. A hole is formed extending from the upper surface of the substrate towards the conducting pads. After the hole is formed, a trench is formed extending from the upper surface towards the lower surface of the substrate, with the trench connecting with the hole. An insulating layer is formed on a sidewall of the trench and a sidewall and a bottom of the hole, and a portion of the insulating layer and a portion of the dielectric layer are removed to expose a portion of the conducting pads. A conducting layer is formed on the sidewall of the trench and the sidewall and the bottom of the hole, electrically contacting with the conducting pads.


Find Patent Forward Citations

Yen, Yu-Lin. (2015). Chip package and method for forming the same (U.S. Patent No. 8951836). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8951836

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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