The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2015
Filed:
Jun. 27, 2012
Charlotte Dewan Adams, Poughkeepsie, NY (US);
Michael P. Chudzik, Danbury, CT (US);
Siddarth A. Krishnan, Peekskill, NY (US);
Unoh Kwon, Fishkill, NY (US);
Shahab Siddiqui, White Plains, NY (US);
Charlotte DeWan Adams, Poughkeepsie, NY (US);
Michael P. Chudzik, Danbury, CT (US);
Siddarth A. Krishnan, Peekskill, NY (US);
Unoh Kwon, Fishkill, NY (US);
Shahab Siddiqui, White Plains, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.