The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2014
Filed:
Dec. 21, 2012
Scott E. Thompson, Gainseville, FL (US);
Lucian Shifren, San Jose, CA (US);
Pushkar Ranade, Los Gatos, CA (US);
Yujie Liu, San Jose, CA (US);
Sung Hwan Kim, Santa Clara, CA (US);
Lingquan Wang, Los Gatos, CA (US);
Dalong Zhao, San Jose, CA (US);
Teymur Bakhishev, San Jose, CA (US);
Thomas Hoffmann, Los Gatos, CA (US);
Sameer Pradhan, San Jose, CA (US);
Michael Duane, San Carlos, CA (US);
Scott E. Thompson, Gainseville, FL (US);
Lucian Shifren, San Jose, CA (US);
Pushkar Ranade, Los Gatos, CA (US);
Yujie Liu, San Jose, CA (US);
Sung Hwan Kim, Santa Clara, CA (US);
Lingquan Wang, Los Gatos, CA (US);
Dalong Zhao, San Jose, CA (US);
Teymur Bakhishev, San Jose, CA (US);
Thomas Hoffmann, Los Gatos, CA (US);
Sameer Pradhan, San Jose, CA (US);
Michael Duane, San Carlos, CA (US);
SuVolta, Inc., Los Gatos, CA (US);
Abstract
A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.