The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2014

Filed:

Dec. 22, 2010
Applicants:

Mark S Hlad, Chandler, AZ (US);

Islam a Salama, Chandler, AZ (US);

Mihir K Roy, Chandler, AZ (US);

Tao Wu, Chandler, AZ (US);

Yueli Liu, Gilbert, AZ (US);

Kyu OH Lee, Chandler, AZ (US);

Inventors:

Mark S Hlad, Chandler, AZ (US);

Islam A Salama, Chandler, AZ (US);

Mihir K Roy, Chandler, AZ (US);

Tao Wu, Chandler, AZ (US);

Yueli Liu, Gilbert, AZ (US);

Kyu Oh Lee, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 23/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.


Find Patent Forward Citations

Loading…