The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2014

Filed:

Apr. 06, 2011
Applicants:

Thomas E. Grebs, Mountain Top, PA (US);

Nathan Lawrence Kraft, Pottsville, PA (US);

Rodney Ridley, Scarborough, ME (US);

Gary M. Dolny, Mountain Top, PA (US);

Joseph A. Yedinak, Mountain Top, PA (US);

Christopher Boguslaw Kocon, Mountain Top, PA (US);

Ashok Challa, Sandy, UT (US);

Inventors:

Thomas E. Grebs, Mountain Top, PA (US);

Nathan Lawrence Kraft, Pottsville, PA (US);

Rodney Ridley, Scarborough, ME (US);

Gary M. Dolny, Mountain Top, PA (US);

Joseph A. Yedinak, Mountain Top, PA (US);

Christopher Boguslaw Kocon, Mountain Top, PA (US);

Ashok Challa, Sandy, UT (US);

Assignee:

Fairchild Semiconductor Corporation, South Portland, ME (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one general aspect, an apparatus can include a trench disposed in a semiconductor region, a shield dielectric layer lining a lower portion of a sidewall of the trench and a bottom surface of the trench, and a gate dielectric lining a upper portion of the sidewall of the trench. The apparatus can also include a shield electrode disposed in a lower portion of the trench and insulated from the semiconductor region by the shield dielectric layer, and an inter-electrode dielectric (IED) disposed in the trench over the shield electrode where the shield electrode has a curved top surface.


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