The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2014
Filed:
Feb. 21, 2013
International Business Machines Corporation, Armonk, NY (US);
Globalfoundries, Inc., Grand Caymon, CI;
Bo Bai, White Plains, NY (US);
Linda Black, Wappinger Falls, NY (US);
Abhishek Dube, Fishkill, NY (US);
Judson R. Holt, Wappingers Falls, NY (US);
Viorel C. Ontalus, Danbury, CT (US);
Kathryn T. Schonenberg, Wappingers Falls, NY (US);
Matthew W. Stoker, Hopewell Junction, NY (US);
Keith H. Tabakman, Fishkill, NY (US);
International Business Machines Corporation, Armonk, NY (US);
GlobalFoundries, Inc, Grand Cayman, KY;
Abstract
A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.