The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2014
Filed:
Mar. 29, 2012
Fei Xie, Sichuan, CN;
Wen Cheng Tien, Sichuan, CN;
Ya Ping Chen, Sichuan, CN;
LI Bin Man, Sichuan, CN;
Kuo Jung Chen, Sichuan, CN;
Yu Liu, Sichuan, CN;
Tian Yi Zhang, Sichuan, CN;
Sisi Xie, Sichuan, CN;
Fei Xie, Sichuan, CN;
Wen Cheng Tien, Sichuan, CN;
Ya Ping Chen, Sichuan, CN;
Li Bin Man, Sichuan, CN;
Kuo Jung Chen, Sichuan, CN;
Yu Liu, Sichuan, CN;
Tian Yi Zhang, Sichuan, CN;
Sisi Xie, Sichuan, CN;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a second opening over a gate stack in a second die area having the top dielectric, a hard mask, and a gate electrode. The top dielectric layer is etched to form a semiconductor contact while etching at least a portion the hard mask layer thickness over a gate contact area exposed by the second opening. An inter-layer dielectric (ILD) is deposited. A photosensitive material is patterned to generate a third opening in the photosensitive material over the semiconductor contact and a fourth opening inside the gate contact area. The ILD is etched through to reopen the semiconductor contact while etching through the ILD and residual hard mask if present to provide a gate contact to the gate electrode.