The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 24, 2014
Filed:
Dec. 13, 2011
Chih-hao Wang, Hsin-Chu, TW;
Shang-chih Chen, Jiadong Township, TW;
Yen-ping Wang, Taipei, TW;
Hsien-kuang Chiu, Hsin-Chu, TW;
Liang-gi Yao, Hsin-Chu, TW;
Chenming HU, Hsin-Chu, TW;
Chih-Hao Wang, Hsin-Chu, TW;
Shang-Chih Chen, Jiadong Township, TW;
Yen-Ping Wang, Taipei, TW;
Hsien-Kuang Chiu, Hsin-Chu, TW;
Liang-Gi Yao, Hsin-Chu, TW;
Chenming Hu, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.