The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2014

Filed:

Dec. 21, 2012
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Ching-Fu Yeh, Hsinchu, TW;

Hsiang-Huan Lee, Jhudong Township, Hsinchu County, TW;

Chao-Hsien Peng, Hsinchu, TW;

Hsien-Chang Wu, Taichung, TW;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/027 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0271 (2013.01); H01L 21/76886 (2013.01);
Abstract

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A conductive layer is deposited on the substrate. A patterned hard mask is formed on the conductive layer and then a patterned photoresist is formed on the patterned hard mask and the conductive layer. A local metal catalyst layer is formed on the conductive layer in the openings of the patterned photoresist. Carbon nanotubes (CNTs) are grown from the local metal catalyst layer. The conductive layer is etched by using the CNTs and the patterned hard mask as etching mask to form metal features. An inter-level dielectric (ILD) layer is deposited between metal features.


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