The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 22, 2014

Filed:

Feb. 27, 2012
Applicants:

Ching-shun Yang, Zhudong Township, TW;

Ze-ming Wu, Tainan, TW;

Hsiao-shu Chao, Baoshan Township, TW;

Yi-kan Cheng, Taipei, TW;

Inventors:

Ching-Shun Yang, Zhudong Township, TW;

Ze-Ming Wu, Tainan, TW;

Hsiao-Shu Chao, Baoshan Township, TW;

Yi-Kan Cheng, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 11/22 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a semiconductor device design method performed by at least one processor, first and second electrical components are extracted from a layout of a semiconductor device. The semiconductor device has a semiconductor substrate and the first and second electrical components in the semiconductor substrate. Parasitic parameters of a coupling in the semiconductor substrate between the first and second electrical components are extracted using a first tool. Intrinsic parameters of the first and second electrical components are extracted using a second tool different from the first tool. The extracted parasitic parameters and intrinsic parameters are combined into a model of the semiconductor device. The parasitic parameters of the coupling are extracted based on a model of the coupling included in the second tool.


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