Method and system for semiconductor simulation

Abstract

An integrated circuit (IC) simulation method comprises providing a device process model from a non-transitory machine readable storage medium into a programmed computer. The device process model includes one or more device variables. Each device variable defines a probability distribution of an active-device-level variation of devices in an IC. A conductive line model and/or a multi patterning technology (MPT) model is provided from the storage medium to the computer. The conductive line model includes one or more conductive line variables. Each conductive line variable defines a probability distribution of a conductive-line process-induced variation. The MPT model includes one or more MPT variables. Each MPT variable defines a probability distribution of a mask-misalignment-induced conductive line coupling variation. A Monte Carlo simulation is performed in the computer, including the device process model and the conductive line model or MPT model, to identify parasitic couplings in the IC.