The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 22, 2014

Filed:

Nov. 05, 2009
Applicants:

Max Liu, Jhubei, TW;

Chao-shun Hsu, San Shin, TW;

Ya-wen Tseng, Hsin-Chu, TW;

Wen-chih Chiou, Miaoli, TW;

Weng-jin Wu, Hsin-Chu, TW;

Inventors:

Max Liu, Jhubei, TW;

Chao-Shun Hsu, San Shin, TW;

Ya-Wen Tseng, Hsin-Chu, TW;

Wen-Chih Chiou, Miaoli, TW;

Weng-Jin Wu, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 29/417 (2006.01); H01L 23/498 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4175 (2013.01); H01L 2225/06541 (2013.01); H01L 23/49822 (2013.01); H01L 21/76898 (2013.01);
Abstract

Through substrate via barrier structures and methods are disclosed. In one embodiment, a semiconductor device includes a first substrate including an active device region disposed within isolation regions. A through substrate via is disposed adjacent to the active device region and within the first substrate. A buffer layer is disposed around at least a portion of the through substrate via, wherein the buffer layer is disposed between the isolation regions and the through substrate via.


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