The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 2014
Filed:
May. 21, 2012
Xiuyu Cai, Albany, NY (US);
Xunyuan Zhang, Albany, NY (US);
Ruilong Xie, Albany, NY (US);
Errol T. Ryan, Clifton Park, NY (US);
John Iacoponi, Wappingers Falls, NY (US);
Xiuyu Cai, Albany, NY (US);
Xunyuan Zhang, Albany, NY (US);
Ruilong Xie, Albany, NY (US);
Errol T. Ryan, Clifton Park, NY (US);
John Iacoponi, Wappingers Falls, NY (US);
GLOBALFOUNDRIES, Inc., Grand Cayman, KY;
Abstract
Methods are provided for forming an integrated circuit. In an embodiment, the method includes forming a sacrificial mandrel overlying a base substrate. Sidewall spacers are formed adjacent sidewalls of the sacrificial mandrel. The sidewall spacers have a lower portion that is proximal to the base substrate, and the lower portion has a substantially perpendicular outer surface relative to the base substrate. The sidewall spacers also have an upper portion that is spaced from the base substrate. The upper portion has a sloped outer surface. A first dielectric layer is formed overlying the base substrate and is conformal to at least a portion of the upper portion of the sidewall spacers. The upper portion of the sidewall spacers is removed after forming the first dielectric layer to form a recess having a re-entrant profile in the first dielectric layer. The re-entrant profile of the recess is straightened.