The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2014
Filed:
Sep. 23, 2009
Tzung-han Tan, Taipei, TW;
Bang-chiang Lan, Taipei, TW;
Ming-i Wang, Taipei, TW;
Tzung-i Su, Yunlin County, TW;
Chien-hsin Huang, Taichung, TW;
Hui-min Wu, Hsinchu County, TW;
Chao-an Su, Kaohsiung County, TW;
Min Chen, Taipei County, TW;
Meng-jia Lin, Changhua County, TW;
Tzung-Han Tan, Taipei, TW;
Bang-Chiang Lan, Taipei, TW;
Ming-I Wang, Taipei, TW;
Tzung-I Su, Yunlin County, TW;
Chien-Hsin Huang, Taichung, TW;
Hui-Min Wu, Hsinchu County, TW;
Chao-An Su, Kaohsiung County, TW;
Min Chen, Taipei County, TW;
Meng-Jia Lin, Changhua County, TW;
United Microelectronics Corp., Hsinchu, TW;
Abstract
An integrated circuit (IC) having a microelectromechanical system (MEMS) device buried therein is provided. The integrated circuit includes a substrate, a metal-oxide semiconductor (MOS) device, a metal interconnect, and the MEMS device. The substrate has a logic circuit region and a MEMS region. The MOS device is located on the logic circuit region of the substrate. The metal interconnect, formed by a plurality of levels of wires and a plurality of vias, is located above the substrate to connect the MOS device. The MEMS device is located on the MEMS region, and includes a sandwich membrane located between any two neighboring levels of wires in the metal interconnect and connected to the metal interconnect.