The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 2014
Filed:
May. 26, 2011
Seshadri Ganguli, Sunnyvale, CA (US);
Sang Ho Yu, Cupertino, CA (US);
Sang-hyeob Lee, Fremont, CA (US);
Hyoung-chan Ha, San Jose, CA (US);
Wei Ti Lee, San Jose, CA (US);
Hoon Kim, San Jose, CA (US);
Srinivas Gandikota, Santa Clara, CA (US);
Yu Lei, San Jose, CA (US);
Kevin Moraes, Fremont, CA (US);
Xianmin Tang, San Jose, CA (US);
Seshadri Ganguli, Sunnyvale, CA (US);
Sang Ho Yu, Cupertino, CA (US);
Sang-Hyeob Lee, Fremont, CA (US);
Hyoung-Chan Ha, San Jose, CA (US);
Wei Ti Lee, San Jose, CA (US);
Hoon Kim, San Jose, CA (US);
Srinivas Gandikota, Santa Clara, CA (US);
Yu Lei, San Jose, CA (US);
Kevin Moraes, Fremont, CA (US);
Xianmin Tang, San Jose, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
Metal gate structures and methods for forming thereof are provided herein. In some embodiments, a method for forming a metal gate structure on a substrate having a feature formed in a high k dielectric layer may include depositing a first layer within the feature atop the dielectric layer; depositing a second layer comprising cobalt or nickel within the feature atop the first layer; and depositing a third layer comprising a metal within the feature atop the second layer to fill the feature, wherein at least one of the first or second layers forms a wetting layer to form a nucleation layer for a subsequently deposited layer, wherein one of the first, second, or third layers forms a work function layer, and wherein the third layer forms a gate electrode.