The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2014
Filed:
Dec. 31, 2009
Alex Kalnitsky, San Francisco, CA (US);
Hsiao-chin Tuan, juDong County, TW;
Liang-kai Han, Taipei, TW;
Uway Tseng, Tai-zhong, TW;
Yuan-chih Hsieh, Hsinchu, TW;
Hung-hua Lin, Taipei, TW;
Alex Kalnitsky, San Francisco, CA (US);
Hsiao-Chin Tuan, juDong County, TW;
Liang-Kai Han, Taipei, TW;
Uway Tseng, Tai-zhong, TW;
Yuan-Chih Hsieh, Hsinchu, TW;
Hung-Hua Lin, Taipei, TW;
Abstract
A method for forming a support structure for supporting and handling a semiconductor wafer containing vertical FETs formed at the front surface thereof is provided. In one embodiment, a semiconductor wafer is provided having a front surface and a rear surface, wherein the front surface comprises one or more dies separated by dicing lines. The wafer is thinned to a predetermined thickness. A plurality of patterned metal features are formed on a thinned rear surface to provide support for the wafer, wherein each of the plurality of patterned metal features covers substantially one die, leaving the dicing lines substantially uncovered. The wafer is thereafter diced along the dicing lines to separate the one or more dies for later chip packaging.