The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2014

Filed:

Feb. 09, 2010
Applicants:

Pi-tsung Chen, Zhubei, TW;

Ming-hui Chih, Luzhou, TW;

Ken-hsien Hsieh, Taipei, TW;

Wei-long Wang, Hsinchu, TW;

Wen-chun Huang, Xi-Gang Xiang, TW;

Ru-gun Liu, Hsinchu, TW;

Tsai-sheng Gau, Hsinchu, TW;

Wen-ju Yang, Hsinchu, TW;

Gwan Sin Chang, Hsinchu, TW;

Yung-sung Yen, Taipei County, TW;

Inventors:

Pi-Tsung Chen, Zhubei, TW;

Ming-Hui Chih, Luzhou, TW;

Ken-Hsien Hsieh, Taipei, TW;

Wei-Long Wang, Hsinchu, TW;

Wen-Chun Huang, Xi-Gang Xiang, TW;

Ru-Gun Liu, Hsinchu, TW;

Tsai-Sheng Gau, Hsinchu, TW;

Wen-Ju Yang, Hsinchu, TW;

Gwan Sin Chang, Hsinchu, TW;

Yung-Sung Yen, Taipei County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed.


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