The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2013
Filed:
Dec. 07, 2011
Ying-nan Wen, Hsinchu, TW;
Ho-yin Yiu, Kln, HK;
Yen-shih Ho, Kaohsiung, TW;
Shu-ming Chang, New Taipei, TW;
Chien-hung Liu, New Taipei, TW;
Shih-yi Lee, Zhongli, TW;
Wei-chung Yang, Pingzhen, TW;
Ying-Nan Wen, Hsinchu, TW;
Ho-Yin Yiu, Kln, HK;
Yen-Shih Ho, Kaohsiung, TW;
Shu-Ming Chang, New Taipei, TW;
Chien-Hung Liu, New Taipei, TW;
Shih-Yi Lee, Zhongli, TW;
Wei-Chung Yang, Pingzhen, TW;
Other;
Abstract
A chip package includes: a substrate; a drain and a source regions located in the substrate; a gate located on or buried in the substrate; a drain conducting structure, a source conducting structure, and a gate conducting structure, disposed on the substrate and electrically connected to the drain region, the source region, and the gate, respectively; a second substrate disposed beside the substrate; a second drain and a second source region located in the second substrate, wherein the second drain region is electrically connected to the source region; a second gate located on or buried in the second substrate; and a second source and a second gate conducting structure disposed on the second substrate and electrically connected to the second source region and the second gate, respectively, wherein terminal points of the drain, the source, the gate, the second source, and the second gate conducting structures are substantially coplanar.