The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 2013
Filed:
Dec. 05, 2011
Sandra Malhotra, San Jose, CA (US);
Kenichi Koyanagi, Higashihiroshima, JP;
Hiroyuki Ode, Higashihiroshima, JP;
Xiangxin Rui, Campbell, CA (US);
Takashi Arao, Higashihiroshima, JP;
Naonori Fujiwara, Kure, JP;
Sandra Malhotra, San Jose, CA (US);
Kenichi Koyanagi, Higashihiroshima, JP;
Hiroyuki Ode, Higashihiroshima, JP;
Xiangxin Rui, Campbell, CA (US);
Takashi Arao, Higashihiroshima, JP;
Naonori Fujiwara, Kure, JP;
Intermolecular, Inc., San Jose, CA (US);
Elpida Memory, Inc., Tokyo, JP;
Abstract
A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly or non-doped material. The highly doped material will remain amorphous (<30% crystalline) after an anneal step. The high band gap material will remain amorphous (<30% crystalline) after an anneal step. The lightly or non-doped material will become crystalline (≧30% crystalline) after an anneal step. The high band gap material is formed between the amorphous highly doped material and the lightly or non-doped material and provides an intermediate barrier to conduction through the multi-layer dielectric stack.