The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2013

Filed:

Jan. 31, 2012
Applicants:

Junjiang Lei, Bellevue, WA (US);

Le Hong, West Linn, OR (US);

Mei-fang Shen, Chupei, TW;

Yining Pan, Zhubei, TW;

Inventors:

Junjiang Lei, Bellevue, WA (US);

Le Hong, West Linn, OR (US);

Mei-Fang Shen, Chupei, TW;

YiNing Pan, Zhubei, TW;

Assignee:

Mentor Graphics Corporation, Wilsonville, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Aspects of the invention relate to techniques for determining edge fragment correlation information. With various implementations of the invention, image intensity slope information for edge fragments in a layout design is determined. The image intensity slope information comprises information describing how image intensity for each of the edge fragments changes with its position. Image amplitude sensitivity information for the edge fragments is also determined. The image amplitude sensitivity information comprises information describing how image amplitude for each of the edge fragments changes with positions of neighboring edge fragments. Based on the image intensity slope information and the image amplitude sensitivity information, edge fragment correlation information for the edge fragments is determined. Using the edge fragment correlation information, the layout design may be processed by using, for example, OPC techniques. This OPC process may be performed on the whole layout design or problematic layout regions identified by a conventional OPC process.


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