The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2013
Filed:
Sep. 07, 2011
Ying-chou Cheng, Zhubei, TW;
Boren Luo, Zhubei, TW;
Wen-hao Liu, Zhubei, TW;
Tsong-hua Ou, Taipei, TW;
Chih-wei Hsu, Zhubei, TW;
Wen-chun Huang, Tainan, TW;
Ru-gun Liu, Hsinchu, TW;
Ying-Chou Cheng, Zhubei, TW;
Boren Luo, Zhubei, TW;
Wen-Hao Liu, Zhubei, TW;
Tsong-Hua Ou, Taipei, TW;
Chih-Wei Hsu, Zhubei, TW;
Wen-Chun Huang, Tainan, TW;
Ru-Gun Liu, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
The present disclosure provides integrated circuit methods for target-based dummy insertion. A method includes providing an integrated circuit (IC) design layout, and providing a thermal model for simulating thermal effect on the IC design layout, the thermal model including optical simulation and silicon calibration. The method further includes providing a convolution of the thermal model and the IC design layout to generate a thermal image profile of the IC design layout, defining a thermal target for optimizing thermal uniformity across the thermal image profile, comparing the thermal target and the thermal image profile to determine a difference data, and performing thermal dummy insertion to the IC design layout based on the difference data to provide a target-based IC design layout.