The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 16, 2013
Filed:
Apr. 12, 2012
Wen-han Hung, Kaohsiung, TW;
Tsai-fu Chen, Hsinchu, TW;
Shyh-fann Ting, Tai-Nan, TW;
Cheng-tung Huang, Kao-Hsiung, TW;
Kun-hsien Lee, Tai-Nan, TW;
Ta-kang Lo, Taoyuan County, TW;
Tzyy-ming Cheng, Hsinchu, TW;
Wen-Han Hung, Kaohsiung, TW;
Tsai-Fu Chen, Hsinchu, TW;
Shyh-Fann Ting, Tai-Nan, TW;
Cheng-Tung Huang, Kao-Hsiung, TW;
Kun-Hsien Lee, Tai-Nan, TW;
Ta-Kang Lo, Taoyuan County, TW;
Tzyy-Ming Cheng, Hsinchu, TW;
United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.