The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 2013
Filed:
Mar. 30, 2010
Hung-pin Chang, Taipei, TW;
Chien-ming Chiu, Hsin-Chu, TW;
Tsang-jiuh Wu, Hsin-Chu, TW;
Shau-lin Shue, Hsin-Chu, TW;
Chen-hua Yu, Hsin-Chu, TW;
Hung-Pin Chang, Taipei, TW;
Chien-Ming Chiu, Hsin-Chu, TW;
Tsang-Jiuh Wu, Hsin-Chu, TW;
Shau-Lin Shue, Hsin-Chu, TW;
Chen-Hua Yu, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.