The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2013

Filed:

Apr. 18, 2012
Applicants:

Wen-han Hung, Kaohsiung, TW;

Tsai-fu Chen, Hsinchu, TW;

Shyh-fann Ting, Tai-Nan, TW;

Cheng-tung Huang, Kao-Hsiung, TW;

Kun-hsien Lee, Tai-Nan, TW;

Ta-kang Lo, Taoyuan County, TW;

Tzyy-ming Cheng, Hsinchu, TW;

Inventors:

Wen-Han Hung, Kaohsiung, TW;

Tsai-Fu Chen, Hsinchu, TW;

Shyh-Fann Ting, Tai-Nan, TW;

Cheng-Tung Huang, Kao-Hsiung, TW;

Kun-Hsien Lee, Tai-Nan, TW;

Ta-Kang Lo, Taoyuan County, TW;

Tzyy-Ming Cheng, Hsinchu, TW;

Assignee:

United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
Abstract

A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer.


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