The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 12, 2013
Filed:
Feb. 25, 2010
Ying-chou Cheng, Zhubei, TW;
Cheng-lung Stanley Tsai, Hsin-Chu, TW;
Tsong-hua Ou, Taipei, TW;
Cheng Kun Tsai, Hsinchu, TW;
Ru-gun Liu, Hsinchu, TW;
Wen-chun Huang, Xi-Gang Xiang, TW;
Ying-Chou Cheng, Zhubei, TW;
Cheng-Lung Stanley Tsai, Hsin-Chu, TW;
Tsong-Hua Ou, Taipei, TW;
Cheng Kun Tsai, Hsinchu, TW;
Ru-Gun Liu, Hsinchu, TW;
Wen-Chun Huang, Xi-Gang Xiang, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
An integrated circuit (IC) design method providing a circuit design layout having a plurality of functional blocks disposed a distance away from each other; identifying a local pattern density to an approximate dummy region, on the circuit design layout, within a predefined distance to one of the functional blocks; performing a local dummy insertion to the approximate dummy region according to the local pattern density; repeating the identifying and performing to at least some other of the functional blocks; and implementing a global dummy insertion to a non-local dummy region according to a global pattern density.