The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2012

Filed:

Aug. 24, 2010
Applicants:

Chiang-cheng Chang, Tiachung, TW;

Hsin-yi Liao, Taichung, TW;

Hsu-hsi Chang, Taichung, TW;

Shih-kuang Chiu, Taichung, TW;

Inventors:

Chiang-Cheng Chang, Tiachung, TW;

Hsin-Yi Liao, Taichung, TW;

Hsu-Hsi Chang, Taichung, TW;

Shih-Kuang Chiu, Taichung, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A fabrication method of a chip scale package includes: disposing a chip on a carrier board and embedding the chip into a composite board having a hard layer and a soft layer; and removing the carrier board so as to perform a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, chip deviation and contamination, etc., all of which may result in poor electrical connection between the wiring layer and the chip electrode pads in the subsequent RDL process and even waste products as a result.


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