The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2012
Filed:
Feb. 05, 2010
Yuan-chang Su, Taoyuan County, TW;
Shih-fu Huang, Hsinchu County, TW;
Ming-chiang Lee, Kaohsiung, TW;
Chien-hao Wang, Hukou Township, Hsinchu County, TW;
Yuan-Chang Su, Taoyuan County, TW;
Shih-Fu Huang, Hsinchu County, TW;
Ming-Chiang Lee, Kaohsiung, TW;
Chien-Hao Wang, Hukou Township, Hsinchu County, TW;
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
Abstract
An embodiment of an embedded component substrate includes: (1) a semiconductor device including lower, lateral, and upper surfaces; (2) a first patterned conductive layer including a first electrical interconnect extending substantially laterally within the first patterned conductive layer; (3) a second electrical interconnect extending substantially vertically from a first surface of the first interconnect, and including lateral and upper surfaces, and a lower surface adjacent to the first surface; (4) a dielectric layer including an opening extending from an upper surface of the dielectric layer to a lower surface of the dielectric layer, where: (a) the dielectric layer substantially covers the lateral and upper surfaces of the device, and at least a portion of the lateral surface of the second interconnect; and (b) the second interconnect substantially fills the opening; and (5) a second patterned conductive layer adjacent to the upper surfaces of the dielectric layer and the second interconnect.