The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2012
Filed:
Jun. 24, 2010
Andrew M. Hawryluk, Los Altos, CA (US);
Emily True, San Ramon, CA (US);
Manish Ranjan, San Jose, CA (US);
Warren Flack, San Jose, CA (US);
Detlef Fuchs, Fair Oaks, CA (US);
Andrew M. Hawryluk, Los Altos, CA (US);
Emily True, San Ramon, CA (US);
Manish Ranjan, San Jose, CA (US);
Warren Flack, San Jose, CA (US);
Detlef Fuchs, Fair Oaks, CA (US);
Ultratech, Inc., San Jose, CA (US);
Abstract
Sub-field enhanced global alignment (SEGA) methods for aligning reconstituted wafers in a lithography process are disclosed. The SEGA methods provide the ability to accommodate chip placement errors for chips supported by a reconstituted wafer when performing a lithographic process having an overlay requirement. The SEGA methods include measuring chip locations to determine sub-fields of the reconstituted wafer over which enhanced global alignment (EGA) can be performed on the chips therein to within the overlay requirement. The SEGA methods further included individually performing EGA over the respective sub-fields. The SEGA methods take advantage of the benefits of both EGA and site-by-site alignment and are particularly applicable to wafer-level packing lithographic processes such as fan-out wafer-level packaging.