San Jose, CA, United States of America

Manish Ranjan

This inventor holds 1 USPTO granted patent. Top assignee: Ultratech, Inc.. Active years: 2012.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Manish Ranjan. Retrieved from https://idiyas.com/inventor/manish-ranjan-nq8fjoqn

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 5.0

ph-index = 1

Forward Citations = 5(Granted Patents)


Company Filing History:


Years Active: 2012

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1 patent (USPTO):Explore Patents

Title: Manish Ranjan: Innovator in Lithography Processes

Introduction

Manish Ranjan is a notable inventor based in San Jose, CA (US). He has made significant contributions to the field of lithography, particularly through his innovative patent related to enhanced global alignment methods.

Latest Patents

Manish Ranjan holds 1 patent for his work on Sub-field Enhanced Global Alignment (SEGA) methods. This patent discloses techniques for aligning reconstituted wafers in lithography processes. The SEGA methods are designed to accommodate chip placement errors during lithographic processes that have overlay requirements. By measuring chip locations, these methods determine sub-fields of the reconstituted wafer, allowing for enhanced global alignment to be performed effectively. The SEGA methods also incorporate site-by-site alignment benefits, making them particularly useful for wafer-level packaging lithographic processes.

Career Highlights

Manish Ranjan is currently employed at Ultratech, Inc., where he continues to develop innovative solutions in the field of lithography. His work has been instrumental in advancing the technology used in wafer-level packaging.

Collaborations

He has collaborated with notable coworkers, including Andrew M. Hawryluk and Emily M. True, contributing to a dynamic and innovative work environment.

Conclusion

Manish Ranjan's contributions to lithography through his SEGA methods highlight his role as a key innovator in the field. His work continues to influence advancements in wafer-level packaging technologies.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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