The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2012
Filed:
Dec. 03, 2010
Timothy H. Daubenspeck, Colchester, VT (US);
Gary Lafontant, Elmont, NY (US);
Ekta Misra, Fishkill, NY (US);
David L. Questad, Hopewell Junction, NY (US);
George J. Scott, Wappingers Falls, NY (US);
Krystyna W. Semkow, Poughquag, NY (US);
Timothy D. Sullivan, Underhill, VT (US);
Thomas A. Wassick, LaGrangeville, NY (US);
Steven L. Wright, Cortlandt Manor, NY (US);
Timothy H. Daubenspeck, Colchester, VT (US);
Gary Lafontant, Elmont, NY (US);
Ekta Misra, Fishkill, NY (US);
David L. Questad, Hopewell Junction, NY (US);
George J. Scott, Wappingers Falls, NY (US);
Krystyna W. Semkow, Poughquag, NY (US);
Timothy D. Sullivan, Underhill, VT (US);
Thomas A. Wassick, LaGrangeville, NY (US);
Steven L. Wright, Cortlandt Manor, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Semiconductor structures, methods of manufacture and design structures are provided. The structure includes at least one offset crescent shaped solder via formed in contact with an underlying metal pad of a chip. The at least one offset crescent shaped via is offset with respect to at least one of the underlying metal pad and an underlying metal layer in direct electrical contact with an interconnect of the chip which is in electrical contact with the underlying metal layer.