The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2012
Filed:
Jul. 27, 2011
Yu-chih Liu, Taipei, TW;
Jing Ruei LU, Taipei, TW;
Wei-ting Lin, Taipei, TW;
Sao-ling Chiu, Hsin-Chu, TW;
Chien-kuo Chang, Zhubei, TW;
Yu-Chih Liu, Taipei, TW;
Jing Ruei Lu, Taipei, TW;
Wei-Ting Lin, Taipei, TW;
Sao-Ling Chiu, Hsin-Chu, TW;
Chien-Kuo Chang, Zhubei, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
Methods for making a substrate for semiconductor packaging with improved warpage and an apparatus. A method includes providing on a die side of a substrate at least one flip chip mounted integrated circuit die. The substrate may include through substrate vias (TSVs). An underfill is dispensed between the integrated circuit die and the substrate. Initially the underfill is left uncured. A thermal interface material is provided on the upper surface of the at least one integrated circuit die. A heat sink is mounted over the integrated circuit die and in thermal contact with the thermal interface material. A thermal cure is performed to simultaneously cure the underfill material and the thermal interface material. In another embodiment, the thermal cure may simultaneously cure an adhesive mounting the heat sink to the substrate. Solder balls are disposed on a board surface of the substrate to form a ball grid array package.